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Installation
Prerequisites
Peripherals/PMODs
Installation
The SoC
The SoC
Top-Level
Top-Level
SoC Architecture
Clocks and Reset
Interrupts
LEDs and Switches
FPGA Resource Utilization
Components
Components
BoxLambda SoC
Wishbone Interconnect
RISCV Ibex Processor
IMEM
RISCV-DBG Debug Core
LiteDRAM Memory Controller
VERA (Wishbone) Graphics
SDSPI SD Card Controller
SPI Flash Controller
Dual YM2149 PSG Sound Core
USB HID Keyboard and Mouse
UART
GPIO
Timer
I2C
RTCC
VS0
DFX Controller
Builds
Builds
BoxLambda Base
BoxLambda DFX (Experimental/Advanced)
Testing
Testing
The Test Bench
The Test Bench
The Test Bench
The System-Level Test Bench
The Component-Level Test Bench
Test Builds
Test Builds
Hello World
DDR Test
VERA Test
SDSPI and FatFS Test
YM2149 PSG, Audio DAC, and ST-Sound Test
USB HID Keyboard and Mouse Test
SPI Flash Test
Timer, UART, and GPIO Interrupt Test
I2C Test
Real-Time Clock and Calendar Test
Reset Test
DFX Test
Invalid Address Test
Ibex Performance Test
The Build System
The Build System
The Gateware Build System
Building the SoC
Software
Software
The Base Platform
The Base Platform
Architecture
Bootstrap
Bootstrap
Bootstrap
Bootloader
The Linker Script
Interrupts
C Components
C Components
About C Components
Register Access Layer
LiteDRAM Initialization
SDSPI
FatFs
ST-Sound
VERA HAL
USB HID
Flash Driver
UART
GPIO
RISC-V
I2C
Real-Time Clock and Calendar
DFX Controller HAL
Common
Test C Components
Test C Components
About Test C Components
Timer
Interrupt Handling
Embedded CLI
Ymodem
Memory and File System CLI
Peek and Poke CLI
J1B HAL
VS0 HAL
The Software Build System
The Software Build System
The Build System
Building the Software
BoxLambda OS
BoxLambda OS
Requirements
Architecture
Memory Layout
Memory Layout
Table of contents
Memory Footprint
OS Top-Level and Boot Sequence
User Interface
Filesystem
Forth
Forth
The Mecrisp Forth Core
The Forth-C FFI
Stack Notation
Forth Word List
Interrupt Handling
Exception Handling
Interpreting
Include
Filesystem Stack
Try It Out
Testing
Testing
Forth Test Suite
The Directory Structure and Build Trees
Tools
Tools
Target.py
The Cross-Compiler
Bender
Debugging
Register and Memory Map
Register and Memory Map
Reset
UART
GPIO
MTIMER
I2C Master
USB HID
SDSPI
SPI Flash
VERA
YM2149
DFX Controller Control Register
DFX Controller Other Registers
LiteDRAM Registers
Memory Map
Misc.
Misc.
Git Workflow
Blog
Table of contents
Memory Footprint
The OS Memory Layout
¶
BoxLambda OS Memory Layout.
Memory Footprint
¶
TBD
