BoxLambda Memory Map¶
Next to memory-mapped registers, BoxLambda includes the following memory regions:
IMEM¶
Low- and fixed-latency read-write internal memory.
- Address Range:
0x00000000-0x00040000 - Size: 256 Kbytes
I2C Master RAM¶
Read-write memory buffer for I2C transfers.
- Address Range:
0x10000300-0x10000400 - Size: 256 bytes
SPI Flash¶
High-latency read-only memory (writable through flash driver API).
- Address Range:
0x11000000-0x12000000 - Size: 16 Mbytes
The flash memory address range is allocated as follows:
0x11000000-0x113fffff: 4Mbytes reserved for bitstreams0x11500000-0x115fffff: 1Mbyte reserved for the bootloader.0x11600000-0x117fffff: 2Mbytes reserved for application software images.0x11800000-0x11bfffff: 4Mbytes reserved for non-volatile data storage.0x11c00000-0x11ffffff: Not allocated.
VERA Sprite Attribute RAM¶
Write-only Sprite attribute RAM.
- Address Range:
0x12001000-0x12001400 - Size: 1 Kbyte
Two banks of 64 entries of the following format:
| Word | 31/15 | 30/14 | 29/13 | 28/12 | 27/11 | 26/10 | 25/9 | 24/8 | 23/7 | 22/6 | 21/5 | 20/4 | 19/3 | 18/2 | 17/1 | 16/0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Word 0 Bits 15-0 | Mode | - | - | - | Address (16:5) | |||||||||||
| Word 0 Bits 31-16 | - | - | - | - | - | - | X | |||||||||
| Word 1 Bits 15-0 | - | - | - | - | - | - | Y | |||||||||
| Word 1 Bits 31-16 | Sprite height | Sprite width | Palette offset | Collision mask | Z-depth | V-flip | H-flip | |||||||||
| Mode | Description |
|---|---|
| 0 | 4 bpp |
| 1 | 8 bpp |
| Z-depth | Description |
|---|---|
| 0 | Sprite disabled |
| 1 | Sprite between background and layer 0 |
| 2 | Sprite between layer 0 and layer 1 |
| 3 | Sprite in front of layer 1 |
| Sprite width / height | Description |
|---|---|
| 0 | 8 pixels |
| 1 | 16 pixels |
| 2 | 32 pixels |
| 3 | 64 pixels |
Rendering Priority The sprite memory location dictates the order in which it is rendered. The sprite whose attributes are at the lowest location will be rendered in front of all other sprites; the sprite at the highest location will be rendered behind all other sprites, and so forth.
Palette offset works in the same way as with the layers.
The active sprite bank is selected by the SBNK bit in the CTRL register.
The Sprite Renderer can render a maximum of 512 sprite pixels per scanline. That corresponds to 64 8-pixel-wide sprites or 8 64-pixel-wide sprites. The 512 sprite-pixel-per-scanline limit is guaranteed regardless of Layer 0/1 configuration or Wishbone bus access load on Video RAM.
VERA Palette RAM¶
Write-only color palette RAM.
- Address Range:
0x12002000-0x12002200 - Size: 512 bytes
The palette translates 8-bit color indexes into 12-bit output colors. The palette has 256 entries, each with the following format:
| Bit 31-12 | Bit 11-8 | Bit 7-4 | Bit 3-0 |
|---|---|---|---|
| - | Red | Green | Blue |
At reset, the palette RAM will contain the following predefined palette:
000,fff,800,afe,c4c,0c5,00a,ee7,d85,640,f77,333,777,af6,08f,bbb
000,111,222,333,444,555,666,777,888,999,aaa,bbb,ccc,ddd,eee,fff
211,433,644,866,a88,c99,fbb,211,422,633,844,a55,c66,f77,200,411
611,822,a22,c33,f33,200,400,600,800,a00,c00,f00,221,443,664,886
aa8,cc9,feb,211,432,653,874,a95,cb6,fd7,210,431,651,862,a82,ca3
fc3,210,430,640,860,a80,c90,fb0,121,343,564,786,9a8,bc9,dfb,121
342,463,684,8a5,9c6,bf7,120,241,461,582,6a2,8c3,9f3,120,240,360
480,5a0,6c0,7f0,121,343,465,686,8a8,9ca,bfc,121,242,364,485,5a6
6c8,7f9,020,141,162,283,2a4,3c5,3f6,020,041,061,082,0a2,0c3,0f3
122,344,466,688,8aa,9cc,bff,122,244,366,488,5aa,6cc,7ff,022,144
166,288,2aa,3cc,3ff,022,044,066,088,0aa,0cc,0ff,112,334,456,668
88a,9ac,bcf,112,224,346,458,56a,68c,79f,002,114,126,238,24a,35c
36f,002,014,016,028,02a,03c,03f,112,334,546,768,98a,b9c,dbf,112
324,436,648,85a,96c,b7f,102,214,416,528,62a,83c,93f,102,204,306
408,50a,60c,70f,212,434,646,868,a8a,c9c,fbe,211,423,635,847,a59
c6b,f7d,201,413,615,826,a28,c3a,f3c,201,403,604,806,a08,c09,f0b
- Color indexes 0-15 contain the C64 color palette.
- Color indexes 16-31 contain a grayscale ramp.
- Color indexes 32-255 contain various hues, saturation levels, brightness levels.
VERA VGA Line Capture RAM¶
Read-only RAM containing one VGA scanline worth of captured pixel data.
- Address Range:
0x12003000-0x12003a00 - Size: 2560 bytes
The memory has 640 entries, one entry per displayed pixel in the captured scanline (VERA always outputs 640x480 VGA). Each entry has the following format:
| Bit 31-12 | Bit 11-8 | Bit 7-4 | Bit 3-0 |
|---|---|---|---|
| - | Red | Green | Blue |
See here for a description of the VGA line capture mechanism.
VERA VRAM¶
Low- and fixed-latency video memory.
- Address Range:
0x12040000-0x12060000 - Size: 128 Kbytes
SDRAM¶
High- and variable latency read-write external memory.
- Address Range:
0x20000000-0x30000000 - Size: 256 Mbytes
Note that the BoxKern allocates region0x2ff00000-0x30000000 to RAM disk usage.