UART

• Wbuart32 Repo, BoxLambda fork, boxlambda branch: https://github.com/epsilon537/wbuart32

• Wbuart32 Submodule in the BoxLambda Directory Tree: sub/wbuart32/

• Wbuart Component in the BoxLambda Directory Tree: gw/components/wbuart

• Wbuart Top-Level: sub/wbuart32/rtl/wbuart.v

• Wbuart Spec:: sub/wbuart32/doc/spec.pdf

ZipCPU comes to the rescue again with a UART implementation with a Wishbone interface. The BoxLambda variant of the wbuart core contains modifications for enabling and clearing specific interrupt events. These modifications are documented in a separate section of the core's spec.

Core Parameters

The Wbuart core is instantiated with the following parameters:

• Rx and Tx FIFO Size: 16 bytes.
• Hardware Flow Control Support: Enabled.
• Initial Setup:
  • 1000000 baud
  • 8 bits/word
  • no parity
  • 1 stop bit
  • Hardware Flow Control disabled

Wbuart Clock Frequency

The Wbuart core is part of the 50MHz System Clock Domain.