Serial Port

ZipCPU comes to the rescue again with a UART implementation with a Wishbone interface. The BoxLambda variant of the wbuart core contains modifications for enabling and clearing specific interrupt events. These modifications are documented in a separate section of the core's spec.

The wbuart core is instantiated without hardware flow control.

Wbuart Clock Frequency

The Wbuart core is part of the 50MHz System Clock Domain.