The Wishbone Interconnect

The Bus, or Interconnect, is the fabric stitching together the SoC internal components. For this project, the two most relevant SoC internal bus specifications are ARM's AXI bus and the Open-Source Wishbone bus.

AXI is very powerful, very popular, and very complex. It scales up well to very big SoCs. However, I don't think it scales down very well to simple SoCs, such as BoxLambda, where low latency and low complexity are more important than high bandwidth and scalability. Hence, for this project, I'm electing to go with Wishbone.

We'll be using Wishbone in Pipelined Mode, as specified in the Wishbone B4 specification.

Bus Width and Clock Frequency

We'll be using a 32-bit data bus.

The Bus Fabric is part of the 50MHz System Clock Domain.